C for embedded controllers

[John S Gwynne]

--------

   In message <199511271542.KAA29352 at po_box.cig.mot.com> , you write:
 
| > execution time:
|
| > hand assembly:
| >                       head/tail/cycles
| > move.b(a1)+,(a0)+     2    2     6(0/1/1)
| > dbra  loop,d0         6    -2    10(0/2/0)
|
| > 6+10-min(-2,2)-min(2,6)=6+10+2-2=16 clock cycles
| 
| > gcc -O3:
| > 			head/tail/cycles
| > move.b (%a0)+,(%a1)+  2    2    6(0/1/1)
| > subq.l #1,%d0	  0    0    2(0/1/0)
| > jbne .L7		  2    -2   8(0/2/0)
| 
| > 6+2+8-min(-2,2)-min(2,0)-min(0,2)=6+2+8+2-0-0=18 clock cycles
| 
| > In this case C and assembly are the same size (the extra 2 bytes for
| > the return should be added to the above assembly); however, the assembly
| > is 11% faster as a result of better pipeline utilization.
| 
| It's faster than 11%! (about 20%), you forgot to REMOVE the instruction fetch
|  cycles
| for MOVE, since after the first iteration, it is no longer fetched!
| I challenge you to use an emulator/logic analyzer and look at the bus cycles.

Could you explain this? 

I just re-read the microsequencer section of the CPU32 manual. 

CPU32 REFERENCE MANUAL page 8-2:
"Each time a change [of flow] occurs, the instruction pipeline must be
flushed and refilled from the new instruction stream..."

CPU32 REFERENCE MANUAL page 8-7:
"When the CPU32 changes instruction flow, the instruction decode
pipeline must begin refilling before instruction execution can
resume. Refilling force a two-clock idle period at the end of the
change of flow instruction."

The 16 and 18 clock cycle times (for two-clock reads and writes) still
look correct to me. How is it (CPU32 right?) not going to "re-fetch" 
the "move"?

                                       John S Gwynne
                                          Gwynne.1 at osu.edu
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