Old ALDL Synchronous format
Gary W Harris
Gary_W_Harris at ccm.ch.intel.com
Tue Jul 16 14:56:43 GMT 1996
Hi all
Someone a bit ago requested the information on the old GM ALDL
synchronous data format. Here is what I know about it:
; The data frame consists of a start pattern of 9 ones, (the frame
; sync pattern) followed by the actual data. Each data word is
; 9 bits, but the first bit is always a 0. Thus, the leading bit is
; stripped away, leaving the 8-bit data byte. MSB is transmitted
first.
; The total frame length is 19 data bytes (?).
;
;
; The following is a list of the bytes in order of reception:
; Note-- the address is controlled by table @ 0d4c5h for type 4E ECU
; an interesting aside--can change RAM/ROM location that is
; monitored by altering address in EPROM table
;
; A/D conversion values based on 256 counts = 5.000 volts (not 255
counts!)
; Thus, 1 bit = 19.53 mv.
;
; ID_HIGH high byte of eprom ID#, location 0d002h
; ID_LOW low byte of eprom ID#, location 0d003h
; IAC current idle air count
; COOLENT coolent temp, deg C= (0.75 x value) - 40
; MPH miles per hour
; MAP manifold air pressure KPA = (0.3125 x value) + 20
; RPM RPM = 25 x value
; TPS throttle position, % = (100 x value) / 255
; INT integrator value
; O2 o2 sensor value, mv = 4.50 x value
; ERR1 error codes byte 1
; ERR2 error codes byte 2
; ERR3 error codes byte 3
; AFSTAT air/fuel status byte
; BATT battery voltage, Volts = value x 0.195
; IOSTAT descrete IO status byte
; KNOCK knock counter (rolls over)
; BLM block learn mode value
; ALDL aldl counter (rolling--frame cntr?)
;
;
;
;
; Use 2 EPA channels to perform the serial input function.
; EPA0 is set-up to detect a falling edge on PORT 1.0, then
; EPA1 is used to sample the bit value in the middle of the
; the BAUD period.
;
;
; 6.250 mS (=1/160 baud)
; |<------------------------------->|
; | |
;
;---------+ +\\\\\\\\\\\\\\\\\\\\+------+ +\\\\\\
; | | data here (1 or 0) | | | next data bit
; +-----+\\\\\\\\\\\\\\\\\\\\+ +-----+\\\\\\
;
; | | | |<--->|<---1.65 mS high always
; | | |
; | | |
; | | +--sample bit here, t=2.400 ms
; |<--->| from falling edge bit start
; |
; +--200 uS start time (low always)
;
;
Cheers,
Gary
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