Schematic of a GM ALDL -> PC converter

[Michael F. Sargent]

I have no idea.  :-)

The level shifting from ALDL levels to RS-232 must be the problem. Async 
communications is very forgiving of clock speed mismatches. It has to be.

	Mike

----------
From: 	owner-diy_efi at coulomb.eng.ohio-state.edu on behalf of John Faubion
Sent: 	Thursday, November 28, 1996 9:49 AM
To: 	diy_efi at coulomb.eng.ohio-state.edu
Subject: 	Re: Schematic of a GM ALDL -> PC converter

> Why bother?
> 
> Serial I/O is designed to be able to handle at least a 5% error in clock
rates 
> between sender and receiver. Using 8228 instead of 8192 is less than 0.5%

> error.
 
Mike if this works then why are there not more people doing this? The
software should be easy and the cable should be easier. Additionally if its
that easy, why did Diacom spend the time to write software to adapt to a
parallel port? 8{)

John Faubion
jfaubion at beaches.net