more C stuff

[peter paul fenske]

Hi Gang

This will be the last include
and I will try my best to disappear..

/* COMDEFS.H                           DRT  v 2.10 950218

   This include file contains most of the definitions
   needed for a PC serial communications program.  It
   should be in the same directory as your source code.
   Place the following statement in your source file:

   #include "comdefs.h"           // note "", not <>!
*/

/* Don't worry about what the following does, but be sure  */
/* to keep it if you might use a different version of the  */
/* Turbo or Borland C/C++ compiler...                      */

#ifdef __cplusplus                /* defined for C++ 3.x   */
  #define __CPPARGS   ...         /* supports C++ 3 & BC   */
#else
  #define __CPPARGS               /* supports C++ 2.x      */
#endif


/* 8259 Priority Interrupt Controller registers and bits   */

#define PIC_ICR 0x20              /* interrupt ctrl reg    */
#define PIC_IMR 0x21              /* interrupt mask reg    */

#define IRQ4M   0x10              /* COM1/3 interrupt mask */
#define IRQ3M   0x08              /* COM2/4 interrupt mask */
#define EOI     0x20              /* End of Interrupt bit  */

#define INT_C   0x0C              /* COM1/3 interrupt no.  */
#define INT_B   0x0B              /* COM2/4 interrupt no.  */


/* Port-specific definitions                               */

#define COM1    0x3F8             /* COM port base address */
#define COM2    0x2F8
#define COM3    0x3E8
#define COM4    0x2E8


/* The following declarations refer to the offset from     */
/* the base address of COMx for each of the 8250 registers */

#define THR 0                     /* DLAB = 0              */
#define RBR 0                     /*        0              */
#define DLL 0                     /*        1              */
#define DLM 1                     /*        1              */
#define IER 1                     /*        0              */
#define IIR 2
#define LCR 3
#define MCR 4
#define LSR 5
#define MSR 6

/* Line control register bit definitions                  */

#define DLAB 0x80                 /* 1 => baud divisor    */
#define SBRK 0x40                 /* 1 => set TX to space */
#define STKP 0x20                 /* 1 => mark or space   */
#define EPS  0x10                 /* 1 => even or space   */
#define PEN  0x08                 /* 1 => enables parity  */
#define STB  0x04                 /* 1 => 1.5 or 2 stops  */
#define WLS1 0x02                 /* 00 = 5; 01 = 6 bits  */
#define WLS2 0x01                 /* 10 = 7; 11 = 8 bits  */

/* Line status register bit definitions                   */

#define TSRE 0x40                 /* TX shift reg empty   */
#define THRE 0x20                 /* TX holding reg ety   */
#define BI   0x10                 /* break detected       */
#define FE   0x08                 /* framing error        */
#define PE   0x04                 /* parity error         */
#define OE   0x02                 /* overrun error        */
#define DR   0x01                 /* RX data ready        */

/* Modem control register bit definitions                 */

#define LOOP 0x10                 /* 1 => local loopback  */
#define OUT2 0x08                 /* set to enable ints   */
#define OUT1 0x04                 /* user output 2        */
#define RTS  0x02                 /* Request to Send o/p  */
#define DTR  0x01                 /* Data Terminal Ready  */

/* Modem status register bit definitions                  */

#define RLSD 0x80                 /* 1 => carrier detect  */
#define RI   0x40                 /* 1 => ring indicator  */
#define DSR  0x20                 /* 1 => Data Set Ready  */
#define CTS  0x10                 /* 1 => Clear to Send   */
#define DRLSD 0x08                /* 1 => change in RLSD  */
#define TERI 0x04                 /* 1 => RI changed 1->0 */
#define DDSR 0x02                 /* 1 => change in DSR   */
#define DCTS 0x01                 /* 1 => change in CTS   */

/* Interrupt enable register bit definitions              */

#define EDSSI 0x08                /* int on RI or RLSD >1 */
#define ELSI  0x04                /* break or data error  */
#define ETBEI 0x02                /* int on THRE -> 1     */
#define ERBFI 0x01                /* int on DR -> 1       */

/* Interrupt identification register bit definitions      */

#define ID1   0x04                /* ID1 ID0 Int. Source  */
#define ID0   0x02                /*  1   1  brk or error */
                                  /*  1   0  data ready   */
                                  /*  0   1  THR empty    */
                                  /*  0   0  RI/RLSD      */
#define IPEN  0x01                /* interrupt pending    */