More VSS

jdzura at csc.com jdzura at csc.com
Thu Oct 1 13:45:02 GMT 1998


Bruce,

Is this correct?

<snip>

100 mile | 2000 pul | 1 hr     |  1 min   |    200000 pulses
---------|----------|----------|----------| = ---------------
 1hr     |   1mi    | 60 min   | 60 sec   |     360 sec
    56 pulses
=   ---------  = 56 Hz
      1 sec

56Hz is the output from the 2000 pulse per mile sender at 100 MPH.

If this is correct, and I suspect it is, the digital stuff I sent you is probably
not appropriate. The slowest crystal oscilator is 1 MHz, which is way too fast for
this application. Sure, we could divide the clock down, but now the design is
increasing in number of chips.

I think the best way to continue is to treat this like a real engineering project.
We need to define the input and outputs for both the 2000 and 4000 pulse systems.
If you can provide them, I will produce the Phase Locked Loop design that will
multiply by 2 and also provide a working design for a divide by 2 circuit.

There has been some mention that one of the signals is DC coupled, and one is AC
coupled, and I remember reading that one may be sinusoidal. I will need those
details, Confirmation of the 56Hz at 100 MPH, the peak to peak levels, and the
waveform of each set of signals.

As soon as those are provided, the PLL design will only take a few days.

Let me know what you think.

Joe D






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