16045154 chip info

[Ludis Langens]

To solve a VSS problem, I just investigated the '45154 chip in a 1227727
ECM.  This chip is used in the '7727, '7730, and '7749 ECMs.  It is
_not_ used in the '7165, '7748, and '7808.  Below is what I figured out
about this chip.

The '45154 is in a 28 pin PLCC package.  The MPU communicates with it
over the SPI peripheral interface.  It has both an input port and an
output port.  It also multiplexes the two styles of VSS input.  Here is
a partial pinout:

 Pin 8   Input bit, to bit %00000001 of the SPI byte.
 Pin 9   Output bit, from bit %10000000 of the SPI byte.
 Pin 10  Output bit, from bit %01000000.
 Pin 11  Output bit, from bit %00100000.
 Pin 12  SPI clock (from MPU).
 Pin 14  GND
 Pin 15  SPI ~CS (from MPU).
 Pin 16  ~LIMP, aka ~RESET.
 Pin 21  SPI MOSI (from MPU).
 Pin 22  Optical (aka digital) VSS input signal.
 Pin 23  Magnetic (aka analog) VSS input signal.
 Pin 26  Selected VSS signal (output).
 Pin 27  SPI MISO (to MPU).
 Pin 28  VCC

The input port bits are transferred to the SPI shift register on the
falling edge of pin 15.  The SPI shift register is transferred to the
output port on the rising edge of pin 15.  The SPI shifter is only 8
bits wide.  If the MPU attempts multiple byte transfers without
releasing pin 15, the previous output byte will simple loop back into
the MPU.

If pin 16 is low, the output bits and VSS mux select will be forced to
0.  Input bits can still be read via the SPI port though.

Bit %00010000 of the output byte selects between the two VSS sources. 
When this bit is set, pin 22 is routed to pin 26.  When clear, the
signal on pin 23 is divided by two - the result is output on pin 26.

Here is how the pins are connected in a '7727/'7730/'7749:

 Pin 8   From Quad Driver U20 pin 1, ~FAULT.
 Pin 9   To U24 ('64992, magnetic VSS interface) pin 10, DivisorA.
 Pin 10  To U24 pin 9, DivisorB.
 Pin 11  To U24 pin 8, DivisorC.
 Pin 12  From U1 (MPU) pin 50.
 Pin 15  From U1 pin 3, bit %10000000 of port $4002.
 Pin 16  From U13 (I/O buffer) pin 20, ~LIMP.
 Pin 21  From U1 pin 49.
 Pin 22  From U13 pin 12, complement of ECM optical VSS input.
 Pin 23  From U24 pin 5, magnetic VSS zero crossing.
 Pin 26  To U2 (TPU) pin 43, VSS1 capture @ $3FC2/$3FE0.
 Pin 27  To U1 pin 48.

The '64992 zero crossing output pulses whenever the magnetic VSS input
crosses zero volts.  This essentially frequency doubles the VSS signal. 
In magnetic VSS mode, the '45154 divides this back to the original
frequency.  The signal it sends to the TPU may, or may not, be in phase
with the ECM's magnetic VSS input.  The TPU "captures" this signal once
per cycle.  In optical VSS mode, the U13's VSS output is sent to the
TPU.  Because the I/O buffer inverts the signal, the TPU input will be
out of phase with the ECM's optical VSS input.

The '64992 outputs several digital VSS signals for use by cruise control
and the instrument cluster.  It has two 2000 ppm and two 4000 ppm output
drivers.  The '64992 can divide the VSS frequency before sending it to
these outputs.  The Divisor[ABC] bits select the divisor.  Note that the
ECM never sees this frequency division internally.  Here are the divisors:

 A B C
 0 0 0  Divide by 1   (ie for a 4000 ppm VSS)
 0 0 1  Divide by 9   (36000 ppm VSS)
 0 1 0  Divide by 7   (28000 ppm VSS)
 0 1 1  Divide by 11  (44000 ppm VSS)
 1 0 0  Divide by 6   (24000 ppm VSS)
 1 0 1  Divide by 10  (40000 ppm VSS)
 1 1 0  Divide by 8   (32000 ppm VSS)
 1 1 1  Divisor disabled, no output

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/