[Diy_efi] RE: Fast A/D and FPGA

[Bevan Weiss]

I would recommend using a watchdog timer of some sort to ensure that if 
things go bad the processor (and FPGA) won't just continue on doing 
anything silly.  A separate dedicated watchdog chip isn't very expensive 
and they're pretty easy to use, the other option (which is nicer in 
terms of board real estate and unit cost) is to implement the watchdog 
timer in the FPGA.

Bevan

> At the moment the fast ADC is a 400K samples/second unit. Depending on scope results on a real engine we should know pretty quickly what the real data rates are going to be. The fast one connects to the future FPGA via parallel connections. The slower ADC's (currently 8 of them) attach to the FPGA via SPI. The FPGA is intended to offload the CPU not only on the collection side but also on the event side - where the FPGA will do things like fire injectors/ignition coils on a 'pre-determined' schedule buy the CPU. If the CPU does not decide an update to state is required the FPGA will just do the pre-computed deeds on schedule.
>
> The tools I personally am using allow for the use of Verilog or VHDL. I lean more towards Verilog myself. Ian can use whatever he wants to use :-)
>
> At some point the FPGA may well have a CPU core in which case the system chip count goes down a bit...
>
>
> James Holland <j_holland at btopenworld.com> wrote: > I'll take that one...
>   
>> The fast A/D is for ion sensing.
>>
>> Only one ADC is needed per bank of cylinders (bank = set of cylinders
>> with non overlapping firing events)
>>
>> I've designed a spec which will probably go onto an FPGA. I'll put it on
>> the website shortly.
>>
>> snip
>>
>>
>>
>>     
>
> That sounds like a good plan. I have used a similar approach a few times. A
> microcontroller and an FPGA can give a huge amount of performance pretty
> cheaply. There's nothing like parallel processing to speed things up and you
> can do a lot of things simultaneously in an FPGA. Are you using VHDL for the
> FPGA design?
>
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