[Diy_efi] RE: Fast A/D and FPGA

[Ian Molton]

Steven Donegan wrote:
> Ian is already on the watchdog timer thing - I am thinking a signal
> from the CPU to the FPGA on perhaps a once/second - hard to imagine
> any steady state situation where a 1 second timer wouldn't be
> sufficient.

Actually the current FPGA design has no WDT in it. it does have a reset 
line - the idea being that if the system WDT fires, all is reset. the 
default FPGA state after reset will be 'do nothing'.

What the system WDT is, is not defined. eventually it'll probably be 
inside the FPGA, along with the rest of the ECU. I expect early on, the 
ARMs own WDT will suffice.

 > However if you have any other thoughts please share them.

Yes, all input is good.