[Bulk] Re: [Diy_efi] Modular approach to EFI controllers

[ian]

On Tue, 2007-10-02 at 02:10 +0800, Mike wrote:
> At 11:47 PM 10/1/07, you wrote:
> >On Mon, 2007-10-01 at 20:37 +0800, Mike wrote:

> When you say a "proper OS" what does that mean ?

Personally, I'd like to run RT linux or something on the thing. but
really, anything that has a nice civilised way to uinterface to a
terminal or PC will do.

its more what CAN be done now - we're not restricted to tiny CPUs with
miniscule RAM and ROM nowadays.

eg. the FFT for the ion sense can be farmed off to an entire process of
its own, etc.

> My thesis back in 1982 was running the CP/M OS on a Z80 at 4MHz,
> when the ignition trigger came in it switched the whole eprom/ram over to
> another bank from the NMI for the CPU, that little bit was done by two
> chips in hardware. The only problem I had was to run the floppy drive
> if the engine was on. So if I needed to dump stuff to floppy I'd kill
> the engine, minor thing in those days as there wasnt that much data
> to save...

Heh. the Archimedes had a problem with floppy virtual DMA and very high
res video - there just wasnt enough bus bandwidth...

> So by "proper OS", you can run anything but might need to be a bit creative
> re what the CPU expects to find in memory and preload alternate "banks"
> in RAM with things like stack return addresses...

I'd rather avoid such hardware hacks - they just shouldnt be needed
nowadays.

(I do like them, indeed I like 'tiny' code, which is part of the reason
I rewrote the bootloader on my ADSL modem :-) )

> If you are worried about ECU size as a result of hand soldering

Not really.

>  then there
> are piggy back boards for a few, but you can do hand soldering of the finest
> ECU's with a little care, you just need a little extra flux because trying to
> rely on the amount in the solder will result in blobs, also some extra flux
> is a great way to force the extra solder to bead up and suck off, escp if it
> happens to bridge a couple of chip smt pins etc

Yup. I've soldered some pretty tiny surface mount stuff before now.

> Not sure I understand how to reply to this one, um, even a V12 has not
> much overlapping in terms of CPU having to do stuff, if it is able to
> initiate an event such as a injector turn on then use the timer to turn things
> off via int. Same for the dwell time for ignition, if a int for dwell happens
> at same time as int for injector then give injector priority, as one uS of
> variance for dwell isnt going to do much...

at 10k RPM thats 0.6 of a degree.

some bike engines will hit 25kRPM now. thats 0.15 degrees.

and if you stack the latency for (say) 5 concurrent (but sequentially
fired as the CPU may well have to process them one by one) events, the
last event is going to happen 3/4 of a degree out from the first one.

Im not so sure about a petrol engine but for some diesels that do
multiple injections per cycle, that kind of resolution would be useless.

> >The ion sensing I've gone as far as to allow four 'cylinder banks' - IOW
> >four cylinders (on seperate banks) can fire at once.
> 
> Isnt the time slice for the ion sense to be pretty short upon spark initiation ?

in theory you could watch each cylinder the whole time bar the actual
spark event.

in practice, 10 degrees either side of ignition should suffice.
probably.

> Whats your estimate of required sample rate and over what period, 10 bit
> A/D for that event would be sufficient are you thinking you need more bits too  ?

its high. we're looking in the realm of 20 degrees or so, and we'd like
to try to get a full samplebuffer (256) each cycle to make the FFT easy
to optimise. At 10kRPM that gives only 0.0012 seconds to take 256
samples, or 214k samples per second.

20 degrees might be too long too, so we might need to talk in terms of half or possibly a tenth of that time - so we could be looking at 2M samples/sec. Experimentation required.

> >Obviously, if your engine doesnt have more than one bank, you only fit
> >one ADC to the board.
> 
> mmmm, Depending on what period of time you need data, one ADC per
> side (bank of 6) for a V12 might be ample, but if you can pin down the ion
> sense period criticality then if the sample window is short you can probably
> get away with one ADC muxed for a full V12... (maybe just ;-)

I dunno. I'd imagine that you can have a V12 with 2 cyclinders firing
simultaneously, or one where each cylinder fires sequentially. both
would need different treatment (possibly)