EPROM emulator

[David A. Cooley]

Mine is a 64K x 8  27C512

-----Original Message-----
From: jgwynne at mrcday.com <jgwynne at mrcday.com>
To: gmecm at efi332.eng.ohio-state.edu <gmecm at efi332.eng.ohio-state.edu>
Date: Friday, February 12, 1999 10:27 AM
Subject: Re: EPROM emulator


>
>
>   In message <36C3FB6F.1446B288 at cruzers.com>, you write:
>
>| The chip count is:
>|  10  '157    muxes  (remember, two banks!)
>|   2  '257    muxes
>|   2  '245    transceivers
>|   1  '74     F/Fs
>|   1  '32     OR gates
>|   1  PIC     microcontroller
>|   1  MAX232  RS232 driver/receiver
>
>My first drawing uses 14 chips (all small chips, except for RAM and
>FLASH, I'm trying to avoid PLD's) + uP support. That's on par with
>your approach which is a little different. I had intended on using loadable
>shift registers to clock our data and reduce the routing.
>
>| Gee, this would be quite impressive, even when using SOP surface mount
>| parts!
>
>Thank you... I once made a board with more than 40 chips too :)
>
>Your point? If it takes 20 we'll use 20... if we can do it in less, we
>will. I have not excluded a dual port RAM design. we need to look at
>part availability and cost before making those decisions.
>
>
>| FYI, the P4's ('165, '727, '730, '748, '749) wire the EPROM's ~CS input
>| to ground.  The ~OE input is driven by the MPU.  It is asserted for
>| reads in the upper 32K of memory.  It is conditioned by an (MPU
>| internal) VMA, so location $FFFF will not be read during address
>| computation cycles.  ~OE asserts in the middle of the E low time.  It
>| deasserts upon the E high-to-low transition.  Thus, ~OE is high for only
>| about 120nS between back to back PROM reads (with a 2^21 Hz E rate.)
>
>Thanks!
>
>I assume that means that none of the P4's used EPROM's larger that 32K?
>
>john
>