RAMCAL design options

[Ludis Langens]

Several of you expressed interest in a MEMCAL with ECM writeable RAM. 
I'm calling this a RAMCAL.  See a previous message for an architectural
overview of how custom software in the ECM could write to RAM without a
~WE signal.  Below are notes for three different implementations of a
RAMCAL.  They work in ECMs using MEMCALs with 27128, 27256, or 27512
type EPROMs.  The ROM mentioned in the designs refers to the EPROM in
the MEMCAL (which is plugged into the RAMCAL's back and used to boot the
ECM.)  All three designs are intended to use a 128Kbyte SRAM.  A 64KByte
RAM would suffice, but the larger RAMs are cheaper and more common.

For anyone not following closely, the RAMCAL is different from the true
EPROM emulator also being discussed on the list.

  ....................................................................

Design 1:  GAL22V10, 74HCT20, 74HCT374, and 128KByte*8 SRAM.

This is the lowest tech design with just the minimum features.  The '20
shrinks eight address lines down to two signals.  The '374 latches the
low eight address lines during normal ROM/RAM reads.  It gates the saved
data onto the data bus during RAM writes (during which time the MPU is
doing a read).

GAL inputs:
  A0 through A3, A8, A9, A14, and A15
  NAND( A4 through A7 )
  NAND( A10 through A13 )
  ~ECMCS
  ~ECMOE
  ~ENABLE (from the GAL output, this clocks the GAL registers)
GAL outputs:
  ~ROMCS
  ~RAMCS
  ~ROMRAMOE (also to '374 CLK)
  ~RAMWE (also to '374 ~OE)
  ~ENABLE (~ECMCS logical ORed with ~ECMOE)
  STATEMACHINEA, STATEMACHINEB (registers)
  SELECT (register)
  RAMA16 (register)

~ENABLE pulses low for each memory cycle.  It needs to be looped back
because the 22V10 cannot clock it's registers with a combination of two
inputs.  Combining ~CS and ~OE into ~ENABLE makes the design safe no
matter how the ECM enables it's EPROM.  The STATEMACHINE outputs do not
connect to anything, they are used internally to detect the special
sequence of memory reads used to do a RAM write.  SELECT chooses between
ROM or RAM for normal memory reads.  RAMA16 is essentially a single bit
output port.  It allows the RAM to be split into two (64KByte) banks. 
All RAM reads and writes go to the same selected bank.

  ....................................................................

Design 2:  GAL6001, 74HCT20, 74HCT374, and 128KByte*8 SRAM.

The GAL6001 can utilize macrocells hidden behind an input pin.  It also
has eight buried macrocells.  This frees up the three STATEMACHINE and
SELECT pins.  That's not enough to remove the 74HCT20.  It is enough to
add dynamic bank switching by driving the RAM's A14, A15, and A16 via
the GAL.  The ECM can then download into a different RAM bank than it is
currently executing out of.

GAL inputs:
  A0 through A3, A8, A9, A14, and A15
  NAND( A4 through A7 )
  NAND( A10 through A13 )
  ~ECMCS
  ~ECMOE
  ~ENABLE (from the GAL output, this clocks the GAL registers)
  SPARE
GAL outputs:
  ~ROMCS
  ~RAMCS
  ~ROMRAMOE (also to '374 CLK)
  ~RAMWE (also to '374 ~OE)
  ~ENABLE (~ECMCS logical ORed with ~ECMOE)
  RAMA16, RAMA15, RAMA14
Buried GAL cells/registers:
  STATEMACHINEA, STATEMACHINEB
  SELECT
  WR16, WR15, WR14, WRSIZE
  RD16, RD15, RD14

SPARE is an unused input.  ~ENABLE still needs to be looped back because
the 6001 "OutputClock" can only come from a pin.  The WRn bits select
one of eight 16K banks, four 32K banks, or two 64K banks for RAM write
cycles.  The RDn bits select the bank (size specified by WRn) to use for
normal RAM reads.

  ....................................................................

Design 3:  Xilinx XC9536 and 128KByte*8 SRAM.

This is the highest tech design and can include several extra features. 
The XC9536 ComplexProgrammableLogicDevice has 34 I/O pins and 36
macrocells, all in a 44 pin package.  This is enough to build in the
functionality of the two 74HCT chips.

CPLD inputs:
  A0 through A15
  ~ECMCS
  ~ECMOE
CPLD outputs:
  ~ROMCS
  ~RAMCS
  ~ROMOE
  ~RAMOE
  ~RAMWE
  D0 through D7
  RAMA16, RAMA15, RAMA14
Buried CPLD cells/registers:
  STATEMACHINEA, STATEMACHINEB
  SELECT
  WR16, WR15, WR14, WRSIZE
  RD16, RD15, RD14

Design 3 includes all the features of design 2.  This leaves ten unused
macrocells to implement additional features.  Two possibilities are:  An
echo mode where all MPU ROM reads also write to the RAM.  (This is why
the ROM and RAM ~OE's are separated.)  A block memory write mode to
allow faster memory filling.

  ....................................................................

Components for #1 and #2 are easy to obtain.  The XC9536 for #3 might be
harder to locate, but DigiKey sells them for $4.75.  The most expensive
design is #2.  The cheapest, once collateral costs are included, is
(surprise!) #3.  A special device programmer is needed for the GALs in
#1 and #2.  #3's XC9536 can be programmed in system via a simple 4 wire
interface.  Special software and four wires to a PC parallel port should suffice.

At this point, a group decision is needed.  Is there enough interest to
proceed?  It seems pretty clear that design #3 is the way to go.  If we
proceed, here are several action items:

Write the PLD program.

  I've done this before, although PLD languages have taken a quantum
leap since then.

Compile the PLD program to a "fuse map".

  Xilinx has a web accessible PLD compiler on their web pages!  They
  may also have software and a design for hardware to program the parts.

Decide on component/connector placement and route a circuit board.

  This will be easy - it is mostly a bus with one chip hanging off the
  side.

Prepare PCB "artwork".

  I'm lost on this item.  It sounds like several people have the
  software tools to do this.

Organize a group buy of PCBs.

Modify several ECM programs to add the needed ALDL commands.

Write a mini-scantool to download RAM images.


So, Yea or Nay?

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/