anyone out there

[Ludis Langens]

"Andrew K. Mattei" wrote:
> 
> I'm having a tough time
> locating a "basic theory of use and operation" guide on PLD's.

Look at something like a GAL22V10.  It is essentially a bunch of
gazillion input AND gates.  Groups of AND outputs are ORed together,
optionally sent through a D F/F, and then through a tri-state driver to
an output.  The ANDs and ORs are enough to implement most combinatorial
logic functions.

> OK,
> really basic question. I "assume" some kind of clock is going to be
> connected to the CPLD - and that based on sequential commands (like
> those above), and a certain logical gate layout, we can vary outputs.

The only "clock" available for this design is the OR of the
EPROM's/MEMCAL's ~CS and ~OE.  This should pulse once per memory cycle. 
That's enough to advance a state machine which pulls the strings to run
everything else.

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/