DRAC simple design

[Carter Shore]

The PLL may not be so simple either, since if the
input is a sine(ish) wave, you must condition it to
digital levels. Then there is the issue of loop
damping, min/max frequency required vs the dynamic
range of your VCO, settling times, start up
strategies, etc. 

> I remember someone telling me about an easier way
> using a simple Phased Lock
> Loop.. but haven't thought much about it.. it may
> use less parts.. but I
> would think my idea should work, and is infinately
> variable to make up for
> inaccurate speedo's
> 
> Kevin Margitta
> 3800 series II s/c, Lesabre T-type, 88
> 
> 


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