Data on 16034984

[Peter Gargano]

Andy Whittaker - Chester UK wrote:
> 
> However, does anyone have details on any of the chips...

I've included some code snippets that access the A/D converter and the FMD
chip. They are from ASBX for the 1227808 ('165). I'd be surprised if your
code is not very similar. I apologise to those who are "code challenged" for 
the size of this post, but I think there are enough people on this list who
are reasonably au fait with GM code (BTW, mnemonics are from my own DHC11
that I will be making available soon).

The A/D chip appears close to a Texas Instruments TLC452 or
Motorola MC145041

 Try:  http://www.ti.com/sc/docs/products/analog/tlc542.html

;
; Read A/D converter - ($ECD8)
;
; In:  A = A/D command
;
; Out: A = A/D result, or 0 if there was an error (check Carry flag)
;      Carry Flag = Clear -> Okay, Set -> Failure
;
; The test channel is used to determine if an error exists with
; the reference voltage - which should return a count of 127
;
ReadADC:
        pushB
        pushX
        ldX     #$4002                  ;parallel I/O port
        bclr    0, X, #bit3             ;Select A/D converter
        call    SpiTxRx                 ;Read, use mux address in A
        tAB                             ;result to B
        ldaA    #7                      ;timer value
@0
        decA                            ;short delay
        bne     @0

        ldaA    #$B0                    ;select the test channel (12)
        call    SpiTxRx                 ;read A/D test channel
        bcs     @1                      ;SPI error?
        cmpB    #127-10                 ;less than 127-10 ?
        bls     @1                      ;no
        cmpB    #127+10                 ;more than 127+10 ?
        bhi     @1                      ;no
        clc                             ;therefore no error
        jr      @2                      ;ok exit
@1
        clrA                            ;error - set result = 0
        sec                             ;show error
@2
        bset    0, X, #bit3             ;deselect A/D converter
        popX
        popB
        ret
;


Here's some code for the FMD...

Note that for ASBX, location $02C holds the Data output byte. Note also
that I have called the "Output byte" (as described by Ludis below) as the 
"first FMD status byte"

Ludis Langens wrote:

> Output byte:
>  bit7: Input source select; 0 == inputs, 1 == status
>  bit6: IRQ enable (IRQ on falling edge of ESTHi)
>  bit5: ??
>  bit4: Pin 8 source; 0 == pin 9 input, 1 == bit3
>  bit3: Pin 8 output data when bit4 is set
>  bit2: EST enable
>  bit1: Limp home watchdog bit
>  bit0: CTS pullup; 0 == 4K ohm, 1 == 348 ohm
> 
> Input byte:
>  bit7: Pin 41 input
>  bit6: Pin 40 input
>  bit5: Pin 39 input
>  bit4: Pin 38 input
>  bit3: Pin 37 input
>  bit2: Pin 36 input
>  bit1: Pin 35 input
>  bit0: Pin 34 input
> 
> Status byte:
>  bit7: ??
>  bit6: Pin 52 input (from injector output)
>  bit5: ??
>  bit4: 0 == 6 or 8 cylinder
>  bit3: 0 == 4 or 8 cylinder
>  bit2: ??
>  bit1: ??
>  bit0: ??
> 
> Once this chip asserts it's IRQ output, the only way to deassert it is
> to write a zero to the IRQ enable bit.
> 
> The watchdog bit needs to be written with alternating values faster than
> a certain rate, otherwise the limphome mode is forced.
> 
> The high bit of the output byte chooses between response bytes
> (input/status) for that very SPI transfer.
> 
> Esoteric data:  The chip select must be dropped and asserted for each
> SPI transfer.  If it isn't, then subsequent SPI transfers simply rotate
> through an internal shift register.  The internal register is only 7
> bits long - the first SPI bit doesn't use the shifter.
> May I first congratulate Ludis on a great, informative site! As some of you
> may well be aware, I'm currently disassembling the ECU code in my Lotus
> Esprit and having the circuit diagram in front of me has been a great help.
> My Lotus ECU is very similar to the 1227727 with four plugs on the outside.

;
; FMDbyte1 ($ED03) - Read the 1st FMD status byte (command bit 7 = 0)
;
FMDbyte1:
        bclr    L002C, #bit7            ;clear bit 7 FMD Command/Output Data b
        jr      FMDio
;
;
; FMDbyte2 ($ED08) - Read the 2nd FMD status byte (command bit 7 = 1)
;
FMDbyte2:
        bset    L002C, #bit7            ;set bit 7 to select 2nd status byte
;
;
; FMDio ($ED0B) - FMD I/O Write and Read the FMD output/status
;
; The FMD is read/written by calling the SPI I/O routine.
; Bit 7 of the command byte selects which status byte is returned
; FMDio is called to output a value, it will return the status byte
; (1st or 2nd) selected by the last FMDbyteX call (unless L00C2 is
; adjusted!)
;
FMDio:
        pushX
        ldX     #$4002
        bset    0, X, #bit2             ;Select FMD (CPU's PORT22 output)
        ldaA    L002C                   ;FMD command/output byte
        call    SpiTxRx
        bclr    0, X, #bit2             ;Deselect FMD
        popX
        ret
;
;
; SpiTxRx - SPI transmit and receive routine ($ED1C)
;
; A holds byte to send to the currently selected SPI device
; The device is assumed to be selected by accessing $4002 and
; setting PORT22 for the FMD, or PORT23 for the A/D chip.
;
; In:   A = Output byte to SPI device
;
; Out:  A = byte received from the SPI device (0 for error).
;       C flag:  Clear = okay,
;                Set   = error
;
SpiTxRx:
        pushX
        staA    L4000                   ;byte to Tx on SPI
        ldX     #L4001
        bclr    0, X, #bit7             ;Clear B7 of $4001 to transmit
        ldaA    #22                     ;timeout value
        clc                             ;Carry Flag = 0
@0
        brset   0, X, #bit7, @1         ;wait until READY=1
        decA                            ;track timeout count
        bne     @0                      ;loop waiting

        sec                             ;timeout! - show error
        jr      @2                      ;error exit, Carry Flag is set
@1
        ldaA    L4000                   ;read byte the SPI returned
@2
        popX                            ;or 0 with Carry Flag set
        ret
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