Schematic of a GM ALDL -> PC converter

[Mark Bjork]

Michael F. Sargent wrote:
> 
> I have no idea.  :-)
> 
> The level shifting from ALDL levels to RS-232 must be the problem. Async
> communications is very forgiving of clock speed mismatches. It has to be.
> 
>         Mike
> 
> ----------
> From:   owner-diy_efi at coulomb.eng.ohio-state.edu on behalf of John Faubion
> Sent:   Thursday, November 28, 1996 9:49 AM
> To:     diy_efi at coulomb.eng.ohio-state.edu
> Subject:        Re: Schematic of a GM ALDL -> PC converter
> 
> > Why bother?
> >
> > Serial I/O is designed to be able to handle at least a 5% error in clock
> rates
> > between sender and receiver. Using 8228 instead of 8192 is less than 0.5%
> 
> > error.
> 
> Mike if this works then why are there not more people doing this? The
> software should be easy and the cable should be easier. Additionally if its
> that easy, why did Diacom spend the time to write software to adapt to a
> parallel port? 8{)
> 
> John Faubion
> jfaubion at beaches.netThe spec for RS232 is (i believe) a logic 1 for any signal below .2v, and 
a logic 0 for any voltage above 2.7v. Therefore, even though RS 232 is 
meant to be -15 and +15, the ALDL signal of 0v (logic 0) and 5v (logic 1) 
will work if the signal is "inverted".

I am not a comm port expert, but from recently checking some serial 
interface databooks, i belive the above is true.

Mark