GM P4 $400x regs
Ludis Langens
ludis at cruzers.com
Thu Dec 10 21:54:10 GMT 1998
trinity at golden.net (Mike) wrote:
> The control registers of the P4-chipset which are mapped to $400x in all P4s
> I've seen...From some work I'm doing on several PROMs concurrently, I see
> that $4009 is the serial receive register, $400A is the serial transmit
> register and $4007 is the SCCR2 (HC11 $102D) equivalent. $4008 appears to be
> the "SCI" status register.
>
> $4008 appears pretty close to bit-for-bit compatible with the standard HC11
> $102E SCSR register except bit 0. Anyone know what this bit is doing?
Here's what I've figured out from reading the code:
r/w $4000 SPI data register
r/w $4001 I/O control register, including SPI control
r/w $4002 I/O port (probably all outputs)
r/w $4003 DDR, probably for $4004
r/w $4004 I/O port
ro $4005 Free running up counter, probably at 32768 Hz
r/w $4006 Interrupt time, IRQ when $4006 == $4005 ( maybe <= )
r/w $4007 SCI control register
ro $4008 Interrupt source flags
ro $4009 SCI RxD register
wo $400A SCI TxD register
wo $400B COP watchdog ($FF)
wo $400C COP watchdog ($00)
r/w == read and write, ro == read only, wo == write only
My $4007, $4009, and $400A uses match your findings. $4008 looks to not
be SCI related at all. It's use matches the use of a similar register
in the C3 chipset. This register contains a bit that indicates that IRQ
is asserted. That's bit zero in $4008. The other bits help determine
the interrupt source - or what events have happened since the previous
read of this register. Reading $4008 deasserts IRQ.
Output bits in $4002:
%10000000 chip select to output only SPI device
%01000000 chip select to in and out SPI device
%00001000 chip select to SPI interfaced ADC
%00000100 chip select to in and out SPI device
%00000010 IAC phase B output
%00000001 IAC phase A output
Output bits in $4004:
%00000100 Enable IAC
--
Ludis Langens ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies: http://www.cruzers.com/~ludis/
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