GM P4 $400x regs

[Mike]

>
>Here's what I've figured out from reading the code:
>
>r/w  $4000  SPI data register
>r/w  $4001  I/O control register, including SPI control
>r/w  $4002  I/O port (probably all outputs)
>r/w  $4003  DDR, probably for $4004
>r/w  $4004  I/O port
>ro   $4005  Free running up counter, probably at 32768 Hz
>r/w  $4006  Interrupt time, IRQ when $4006 == $4005  ( maybe <= )
>r/w  $4007  SCI control register
>ro   $4008  Interrupt source flags
>ro   $4009  SCI RxD register
>wo   $400A  SCI TxD register
>wo   $400B  COP watchdog ($FF)
>wo   $400C  COP watchdog ($00)
>

Thanks for responding Ludis,

Yes, a write of #$FF00 to $400B I surmised was a COP reset mechanism.
Interesting...I guess then that the COP in these things is an external timer
that must be periodically updated or the processor reset line would be
asserted. This is opposed to the HC11 which uses the 55/AA write sequence to
the COPRST register which is internal to the proc. Weird.

>
>My $4007, $4009, and $400A uses match your findings.  $4008 looks to not
>be SCI related at all.  It's use matches the use of a similar register
>in the C3 chipset.  This register contains a bit that indicates that IRQ
>is asserted.  That's bit zero in $4008.  The other bits help determine
>the interrupt source - or what events have happened since the previous
>read of this register.  Reading $4008 deasserts IRQ.
>

The interrupt handler examines 4008 and runs serial receive or transmit
routines (or sets up RX and TX hardware) using 4008 to determine if the
source of the interrupt was. I suspect 4008 then does this (including your
$01 bit):

4008 : 80-TDRE
       40-TC
       20-RDRF 
       10-? 
       08-overrun
       04-noise flag
       02-framing error
       01-periodic interrupt

During the receive routine, the status register at 4008 is read and if any
of bits 3, 2 or 1 (#$0E) are set, the receive operation is aborted,
presumably a safing response to a bad character received on the serial line.
This is exactly the bits looked at when I write SCI routines for the HC11 to
see if any of the OR, NF or FE bits are set. That's why I saw 4008 as a copy
of the SCSR register.

Now that I look at these again, I think you're right about 4006 it and the
rate at which 4005 counts up - 32.768kHz. At the start of the routine at
B38D 4006 is read, #$CD (205) is added to it and the value written back to
4006. 205*30.518uS (the period of 32.768kHz) is 6.25mS or so. This number
rings a bell for some reason...where the heck have I heard this number before? 

So I guess the ISR that I thought was solely for the "SCI" system also
serves as the handler for this periodic timer interrupt ("output compare" if
you will) for 4005 & 4006. Cool. That makes things a bit clearer.


>Output bits in $4002:
> %10000000  chip select to output only SPI device
> %01000000  chip select to in and out SPI device
> %00001000  chip select to SPI interfaced ADC
> %00000100  chip select to in and out SPI device
> %00000010  IAC phase B output
> %00000001  IAC phase A output
>
>Output bits in $4004:
> %00000100  Enable IAC
>

I had 4000, 4001 and 4002 pegged as, in part at least, A/D converter control
registers. I had xxxx1xxx in 4002 as an A/D chip select of some sort (0 =
selected or enabled). I had 1xxxxxxx in 4001 as a start-conversion bit (when
driven low). In older P4s I've looked at, if this bit fails to go high after
a short period of time, code 55 (if I remember correctly...) got set
indicating a failed A/D unit. I thought 4000, at least maybe the upper 4 or
5 bits, were a mux or channel select during writes and during reads, was the
A/D result.

Anyhoo, thanks for the 411 on bit 0 of 4008. That helps clear up a few things :)


-----
 Mike