GM (160)23262 A to D chip

[Ludis Langens]

Has anyone figured out all the registers/bits of the A to D chip used in
most (all?) GM C3 ECMs?  This 28 pin DIP is usually marked with the part
number 23262.  I have a question about one control bit.  First, here's
what I've figured out:

\/\/\/

Offset 0 - read (only) : A2D conversion result register

  bit  15   : conversion complete (1)
  bits 14-8 : 0
  bits 7-0  : conversion result (0 to 255)

Offset 2 - write : A2D Control/Status register

  bits 15-9 : unused, written as 0
  bit  8    : start conversion (1)
  bit  7    : unknown
  bits 6-4  : unused, written as 0
  bits 3-0  : mux selector (0 to 15)

Offset 2 - read : A2D Control/Status register

  bit  15   : analog channel 15 > ~1.4 volts
  bit  14   : analog channel 14 > ~1.4 volts
  bit  13   : analog channel 13 > ~1.4 volts
  bit  12   : analog channel 12 > ~1.4 volts
  bit  11   : analog channel 11 > ~1.4 volts
  bit  10   : analog channel 10 > ~1.4 volts
  bits 9-6  : mux selector (0 to 15)
  bits 5-0  : 0


Only analog channels 0, 2 to 5, and 10 to 15 are implemented/bounded
out.  Channel 1 appears to be internally connected to VCC.  Channels 6
to 9 are not connected and float at random intermediate voltages.

All writes need to be performed as a 16 bit write, single byte writes
are ignored.  An 8 bit read will transfer the upper byte (bits 15-8) of
the selected register.

A hardware reset clears the conversion complete flag, clears the
conversion result to 0, and switches the mux to channel 0.

A (word) write to the Control/Status register clears the conversion
complete flag, even if the start conversion bit was not set.  The
conversion result byte retains a previous value until a new value is
loaded (and the conversion complete flag is set.)  The following code
fragment demonstrates the earliest cycle in which the conversion
complete flag will be set.

    LDD #$0100
    STD $1002
    MUL        ; waste 10 E cycles
    MUL        ; waste 10 E cycles
    NOP        ; waste 2 E cycles
    LDD $1000  ; burn 3 E cycles, then read $1000
    BPL HardwareError
    STAB ChannelZeroResult

/\/\/\

What does bit 7 of control register writes do?  I have been unable to
observe any effects of this bit.

Several ECMs always write a zero into this bit.  Several other ECMs
always write a one.  This is done in the A2D subroutine by ORing the mux
selector with a RAM variable.  This variable is initialized to 0x80 and
never changed.

Bit 7 does not:  Alter the conversion time.  Cause any change in the
conversion results.  Cause anything to appear in the "0" read bits.

This chip has two VCC and two GND connections.  The GNDs are both wired
together.  The VCCs are both connected to the VCC supply, though with
seperate circuit board traces (double sided board.)  Perhaps bit 7
switches the full scale reference voltage between the two VCCs.

Perhaps bit 7 turns on/off a high impedance pull-up on the analog
inputs.  This might simplify using channels 10 to 15 as digital inputs. 
However, the pull-up would have to be a very high impedance.  (Most
inputs to the A to D chip are from high impedance sources.  See two
paragraphs back.)

The ECMs which clear bit 7 have at least one digital input via the A to
D chip.  ECMs which set bit 7 don't.  However, the clearing ECMs also
have serious code space limitations.

The bit 7 ORing might be left over from prototype and or special
calibrator hardware.  This is consistent with the initialized but never
changed RAM variable.

Does anyone have any other ideas/information?

               unsigned long BinToBCD(unsigned long i) {unsigned long t;
Ludis Langens     return i ? (t = BinToBCD(i >> 1), (t << 1) + (i & 1) + 
ludis at cruzers.com            (t + 858993459 >> 2 & 572662306) * 3) : 0;}