Pulse doubler schematic

[Ludis Langens]

jdzura at csc.com wrote:
> If the ECM uses a zero crossing detector, does that mean all the signals are AC.
>       Also, what is the Peak to Peak Voltage level? Do we have any idea of what
>       minimum pulse width the ECM can detect?

Many C3 ECMs, like the 1226870 and 1227148, use a timer chip (TPU?)
marked 16023263.  One of its functions is to measure the VSS pulse
interval.  The 16023263 records the time of the pulse's rising edge. 
Because the ECM input buffer also inverts, this is the falling edge of
the 12 volt DC 2000 ppm VSS input to the ECM.  Software takes the
difference between two samples to compute the interval.

The 16023263 measures in units of 65517 3/16 Hz.  The VSS sampling
appears to be delayed by 90 of these clocks.  This may be an internal
TPU latency, or a delay to "debounce" the signal.  So, 90 / 65517 is
about 1.37 mS.  The 90 cycles might include a computational delay in a
(unrelated) PWM output.  More O'scope work is needed...

Newer ECMs might not have exactly 1.37 mS of delay, but that should be
in the ballpark of the minimum pulse width.

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/