DDL - faster Nernst cell sensing

Bernd Felsche bernie at innovative.iinet.net.au
Tue Nov 13 20:11:54 GMT 2001


bcroe at juno.com tapped away at the keyboard with:

> On Sat, 10 Nov 2001 11:47:44 +0800 (WST) Bernd Felsche
> <bernie at innovative.iinet.net.au> writes:
> > See http://bernd.felsche.org/tech/EFI/DDL/DDL.html for the few
> > circuit changes required to implement the fast switching detection,
> > largely eliminating the bandwidth limitations imposed by ADC and
> > subsequent numerical comparisons. Response bandwidth for the
> > controller now approaches 1 MHz compared to the 15kHz or so limit of
> > the ADC strategy for Nernst cell voltage detection.
> > 
> > Furthermore, the detection method lends itself to a simpler control
> > strategy for applying pump pulses (e.g. bang-bang control relying on
> > sensor hysteresis), as well as the ability to measure intrinsic
> > sensor characteristics such as ion migration delays. Cell
> > contamination and other age determinants can thus be quantified.

> I guess you could just "hunt" for a .45 volt crossing
> like an ordinary ECU does.  But you will still need to

i.e. bang-bang control within the hysteresis of the ADC.

Hunting for the reference level is also what's done in all the WB
controllers, even the commercial ones. :-)

> consider the sensor delay in your software, to build
> a stable closed loop.  You will not need anything
> like 1 mhz; 15 khz is probably plenty.

Practical bandwidth of the _controller_ will likely be in the range
of 100 to 250 kHz, once pump circuit operation is taken into
account. These are estimates based on typical pulse timings, CPU
cycles required, etc. As the sensor's response is unknown, it's
hoped that the controller will still be several times faster than
the sensor to give at least the possibility of stable operation.

The controller's response to changes in voltage at the Nernst cell
by ADC alone is 15kHz - the time required for two (8-bit)
conversions and comparison. This leaves no ADC capacity for Ip
measurement.

Using the comparator against the desired reference level means that
the controller can detect and act in just over 4 CPU cycles - the
interrupt response plus another few instructions to effect the
change (reverse pump direction). i.e. 1MHz vs 15kHz

An elaboration of the circuit could be to use a programmable
resistance (instead of potentiometer) to set the desired reference
level for variable hysteresis. This is obvious, but needs to be said
to frustrate somebody putting a patent on it. :-)

> I would think with a single crossing point detector
> and no knowledge of error size, you would need 
> to considerably degrade the sensor feedback 
> loop response.  Probably just run a simple (and
> slow) integrator.

The error size can be evaluated by ADC conversion and comparison.
The ADC channels are already allocated for resistance measurement
for temperature stabilisation. The crossing detector provides for a
rapid response to a transition. It's the knock on the door, so to
speak.

> If you came up with a "negative" pulse Ip generator,
> you might be able to dispense with the virtual
> ground.  The negative pulse could be generated 
> with capacitive coupling from all positive circuitry
> since it is just a fixed digital pulse.  Not so easy 
> to do with a straight analog drive.

The negative pulse generator needs to have it's magnitude measured.
Pump cell resistance is also to be measured for temperature and age.
The temperature sensing pulses have to have a minimum duration to
allow for one complete conversion and a subsequent sample.

Measuring a negative pulse with the ADC on positive rails? Not
without a lot more glue; unless you have a simple suggestion. Your
component budget is 4 components costing no more than $5 in total.
:-)

That's the cost of the floating reference.

-- 
Bernd Felsche - Innovative Reckoning, Perth, Western Australia

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