[Diy_efi] Re: Reversing EPROM decryption board

[Stevan Glogovac]

Don,
   
  just checked: /CS is kept low all the time, /OE is the only one moving... Whenever the EPROM area is accessed, the /OE goes low... Does it change something? I mean, as long as NVRAM's /W is connected to the /OE, it should be fine.. or?
   
  Unfortunatelly, I am not able to control the address lines, I was controlling them only by software...
   
  The rest is clear... I will make the board over weekend and let you know how it went. Hopefully I won't fry the ECU :)).
   
  Regards,
NG
  ----------------------------------------------------------------------------------------------------------------
  Conceptually this is correct but check all of the timing specs. For NVRAM,
make sure it is fast enough and if there is only one bank of EPROMs, make
sure the /CS is actually moving. You will be loading the address & data
busses with more capacitance but only one or two more chips should be fine.
You'll probably want to gate the RAM /CS for a clean shutdown.
It sounds like you are already driving the address lines, so if you can
control
the control signals as well, then there should be no speed or timing problems.

Address sequencing may be checked by rules like: address are sequential unless
a branch or data access is seen, ISR vectors are constant, etc.

-- Don


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