[Bulk] Re: [Diy_efi] Modular approach to EFI controllers
Mon Oct 1 12:37:59 UTC 2007
Something doesnt quite gel in all those calcs, when I do a back of the envelope
event schedule I get a far easier less tortuous branch path. I'm not saying an
FPGA inst good to have to off load the CPU but having done very short int ack
routines and state logic I dont feel its that necessary.
btw: Have you had the chance to draw a 16 line (W16 type) event schedule
and factor in the perishable nature of the data set and fact you wont need
sequential ion samples from all cycles at that 10K rpm rate ?
But, sure once you do a FPGA to handle a W16 then it will of course be backwards
compatible with other engines no problem given a scalable register/inst set etc.
And good to have it as a redundant timer in event cpu fails,
btw: What sort of amortised cost does one end up with for such an FPGA, just broad
brush estimates at this stage and the hard outgoings to get it up to a spec ?
At 07:18 PM 10/1/07, you wrote:
>On Mon, 2007-10-01 at 18:20 +0800, Mike wrote:
>> BTW: Curious, does the W16 have a coincident firing event ?
>I actually dont know.
>I speccd up a bit of overkill really but it never hurts.
>I designed the FPGA so that it can handle timing the reading of up to
>four ADCs at once and driving 2x spark and 2x injectors for up to 16
>My personal application will be a inline 6 with single spark and *maybe*
>dual injectors per port (more likely single)
>but thats the nice thing about FPGAs - you can scale the design up or
>down to suit - *IF* the original design is good enough.
>the idea is that no matter how 'full fat' you make the FPGA, as long as
>it follows the register spec I wrote, it'll work with the same software
>running on the ARM as any other FPGA running any other 'fattness' of the
>(even so, theres a lot of events...)
>for one cylinder: (2xspark, 2x injectors)
>10k RPM = 166 RPS
>so thats potentially:
>42 TDC interrupts (84 if you dont ignore the TDC on compression)
>84 spark events
>84 injection events
>42 ion sense 'data ready' interrupts.
>total 252 events
>multiply by 16 cylinders...
>but thats not the whole story because if you werent using the FPGA you'd
>have to handle some kind of bus for the ion sense ADCs, along with
>thousands of interrupts per event, and also the injection needs to be
>started and stopped, which means you need precise, uS grade timing from
>the ARM and _no_ latency, whilst its doing all that other stuff like
>calculating FFTs of the ion sense data etc.
>not to mention that the FPGA can happily handle things like generating
>fraction-of-a-degree interpolation of the crank angle without any need
>for intervention from the ARM.
>basically it makes sense to have the system split into a timing
>controller thats bullet proof and has no other requirements but to
>calculate crank angle and injection / spark timing, and let the ARM
>handle feeding it instructions, which can be done on a much more
>leisurely basis - and if the ARM freezes, the TC can simply call a stop
>to things before your engine fries (hard watchdog).
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