[Bulk] Re: [Diy_efi] Modular approach to EFI controllers

[ian]

On Mon, 2007-10-01 at 20:37 +0800, Mike wrote:
> 
> Something doesnt quite gel in all those calcs, when I do a back of the
> envelope event schedule I get a far easier less tortuous branch path.

Do share...

>  I'm not saying an FPGA inst good to have to off load the CPU but
> having done very short int ack routines and state logic I dont feel
> its that necessary.

Well spark timing and so on could be done, but I want to run a proper OS
on the CPU, and thats going to muck up interrupt latency unless I waste
a lot of time going RT. Im sure it *can* be done, I just dont want to
and dont feel that doing it all on the CPU gives as neat or robust a
design.

besides, for the W16 twinspark twininjector engine, the timing
controller needs about 90-odd pins of output, and finding nice small CPU
packages that arent hard to solder with THAT much GPIO (before you add
anything else into the mix!) is not so easy.

> btw: Have you had the chance to draw a 16 line (W16 type) event
> schedule and factor in the perishable nature of the data set and fact
> you wont need sequential ion samples from all cycles at that 10K rpm
> rate ?

well with the exception of ion sensing, the 'overlapping' nature of
which depends on the exact engine configuration, all the other events
happen that often, per cylinder, per cycle. You could lose a lot of
spark events with a wasted-spark system but that just doesnt fit my idea
of 'neat'.

The ion sensing I've gone as far as to allow four 'cylinder banks' - IOW
four cylinders (on seperate banks) can fire at once.

Obviously, if your engine doesnt have more than one bank, you only fit
one ADC to the board.

> But, sure once you do a FPGA to handle a W16 then it will of course be
> backwards compatible with other engines no problem given a scalable
> register/inst set etc. And good to have it as a redundant timer in
> event cpu fails,

:-)

> btw: What sort of amortised cost does one end up with for such an
> FPGA, just broad brush estimates at this stage and the hard outgoings
> to get it up to a spec ? 

To be honest, I expect that the timing generator will fit easily into a
CPLD, FPGA is probably overkill (I have a habit of calling all field
programmable logic stuff FPGAs, my bad.

CPLDs are cheap.

That said, whilst cheap is good, I prefer maintainable / clean / robust,
since this is a more or less non commercial project...