EPROM emulator

[thergen at svn.net]

A Cypress cy7c008 or cy7c009 might work
http://www.cypress.com/cypress/prodgate/dual/cy7c019.htm

Accesses to the same address at the same time are a problem.  Since
there's probably no way to make the ECM cpu wait, collisions would have to
be avoided altogether or the ECM cpu should be able to terminate the other
sides memory cycle if needed. The rams mentioned have access times of 20ns
or lower compared to the 120ns needed, which may help in the logic design
for the collision handling. 

Who wants to solder the 100 pin TQFP package to the board? ;)

Tom

On Fri, 12 Feb 1999, Ludis Langens wrote:

> Ron Gregory wrote:
> > 
> > I'm not an EE by any means, but why not try
> > to use a Dual-port RAM?
> > I heard they aren't too expensive any more...
> > at least the "slow" ones we'd use...
> 
> I hope it is intended to use dual port RAM.  A dual bank 27C512 emulator
> w/EPROM built with conventional RAM would require:
> 
> Each RAM bank needs to be a seperate 64KByte SRAM.  Each SRAM's 16
> address lines need to be muxed between the ECM or PIC.  This will take
> four "quad 2to1 muxes".  The RAM control lines also need to be muxed, so
> add a fifth mux.  The ECM needs to be able to read (only) from either
> bank, so add a pair of "quad 2to1 tristate muxes".  The PIC needs to
> read and write either bank, so add a pair of octal transceivers.  Place
> the EPROM on the ECM side of all this logic.  Two D flip flops can
> syncronize the bank switching, one for a bank select, the other being an
> EPROM select.  Clock the F/F's with the OR of the ~CS and ~OE signals
> from the ECM.  The tristate mux can be enabled by ORing Q of the EPROM
> select F/F with (~CS OR ~OE).  The EPROM can be selected similarly,
> except using the notQ output.  The bank select F/F's Q and notQ can
> drive all the mux selector inputs.
> 
> The chip count is:
>  10  '157    muxes  (remember, two banks!)
>   2  '257    muxes
>   2  '245    transceivers
>   1  '74     F/Fs
>   1  '32     OR gates
>   1  PIC     microcontroller
>   1  MAX232  RS232 driver/receiver
> 
> Gee, this would be quite impressive, even when using SOP surface mount
> parts!  Perhaps there are some DRAM controllers that could replace the
> sea of '157's.
> 
> 
> FYI, the P4's ('165, '727, '730, '748, '749) wire the EPROM's ~CS input
> to ground.  The ~OE input is driven by the MPU.  It is asserted for
> reads in the upper 32K of memory.  It is conditioned by an (MPU
> internal) VMA, so location $FFFF will not be read during address
> computation cycles.  ~OE asserts in the middle of the E low time.  It
> deasserts upon the E high-to-low transition.  Thus, ~OE is high for only
> about 120nS between back to back PROM reads (with a 2^21 Hz E rate.)
> 
> -- 
> Ludis Langens                               ludis (at) cruzers (dot) com
> Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/
>