EPROM emulator

[steve ravet]

jgwynne at mrcday.com wrote:
> 
>    In message <Pine.LNX.3.96.990212020658.14316A-100000 at svn.net>, you write:
> 
> | A Cypress cy7c008 or cy7c009 might work
> | http://www.cypress.com/cypress/prodgate/dual/cy7c019.htm
> |
> | Accesses to the same address at the same time are a problem.  Since
> | there's probably no way to make the ECM cpu wait, collisions would have to
> | be avoided altogether or the ECM cpu should be able to terminate the other
> | sides memory cycle if needed. The rams mentioned have access times of 20ns
> | or lower compared to the 120ns needed, which may help in the logic design
> | for the collision handling.
> 
> We need a price quote.
> 
> Approach #3.... time multiplex bus cycles with a single fast
> (single port) SRAM. Probably almost 1/2 the chip count, all cheap and
> readily available. I'll sketch up something to get a better idea of
> the part count... Any other approaches?
> 
> john

Maybe I'm missing something here...  What I thought we were talking
about was a box with a flash and an SRAM.  You could download a PROM
image to the RAM while the engine is running, and also dump the image to
the flash.  The flash can probably hold several PROM images at once. 
Timing is such that none of this interferes with normal operation of the
ECM.  Is that more or less the vision?

If that's the case then I think there's a much simpler solution.  Just
run the address lines and data lines to both the SRAM and flash.  CS is
grounded on both chips.  OE goes to each chip, gated with an OR (cheap
multiplexer).  The control lines for the ORs come from the PIC, via a
flop clocked by the rising edge of OE.  The PIC can switch banks at any
time, the flop ensures that banks are only switched when there is no
access active.

It would also be nice to have some LEDs to indicate which image is
active, and some buttons to switch between them.

This seems workable to me.  The flop on OE enable means there isn't any
timing critical code in the PIC.  The PIC is free to watch the serial
port for data or commands, and to write to the RAM as necessary.  Not
sure how dual port RAM works, can you read and write via both ports?  If
so the only possible timing problem might be simultaneous access to the
same address.  Probably not a big deal, and if you had two RAM banks you
could download to one and read from the other and there wouldn't be any
problems.  They'd be regular SRAMS also.

Is it workable?  I see a PIC, a flop, an inverter, 2 OR gates, and maybe
some buffers for address and data.  7 chips or so.

That's probably had to read, if I can find something to draw schematics
with I'll draw some up and send them out.

--steve


-- 
Steve Ravet
steve.ravet at arm.com
Advanced Risc Machines, Inc.
www.arm.com