EPROM emulator

[Ludis Langens]

Mike Pitts wrote:
> 
> If you find one let us know.  I couldn't find one so I
> customized the '$04' command.

The Australian system added a memory write command, I think as the '$0B'
(11) command.

> I like the idea of SRAM and a one wire mod.  If someone figures
> out how to do this, please let us know.  Like I said, I already
> have an ALDL memory write command.

I'd prefer a zero wire "mod".  Yes, the one wire mod needs just one
pico-hook, but will you remember where to hook it a year from now?  It
is also likely to come loose at the worst possible time - like during a
drop clutch start at the drag strip.

It is possible to build a zero wire "mod" SRAM MEMCAL with a 74__374
octal tri-state F/F and a 24 pin PAL, or with a single 44 pin EPLD.  The
CPU "writes" to the SRAM using a special sequence of ROM reads.  Here's
one possibility:

 ROM cycle 1:  Read magic location A
 ROM cycle 2:  Read magic location B
 ROM cycle 3:  Read from the 256 byte magic memory page D
                 The latch captures the low 8 address bits
 ROM cycle 4:  Read from the desired memory location
                 The latch gates it's contents onto the data bus
                 (The address bus is being driven by the CPU)
                 The SRAM is given a ~WE strobe, thus writing a byte

Here's a sequence to switch between SRAM banks or the boot EPROM:

 ROM cycle 1:  Read magic location A
 ROM cycle 2:  Read magic location B
 ROM cycle 3:  Read from the 256 byte magic memory page C
                 Several low address bits specify the desired bank

If the ROM cycles do not happen in exactly this order with no
intervening ROM cycles, the PAL state machine reverts to looking for
another "cycle 1".  This means that the software which performs these
cycles must not execute from the MEMCAL ROM (or SRAM).  Thus the SRAM
write command must copy a short stub into ECM RAM.  13 bytes of self
modifying code is all that is needed.

Magic location B should be one less than A.  This makes it impossible to
trigger an SRAM write via ROM executed loads (LDD, LDAA, etc.). 
Location B should also be known to never contain code, like an interrupt
vector.  I'm proposing A: $FFFD, B: $FFFC, C: $FCxx, D: $FDxx.

A side affect of this complicated sequencing is that the SRAM is quite
well write protected from random memory writes!


Is there enough group interest to build both a MEMCAL like this and a
true EPROM emulator?

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/