Eprom Emulator

[Ludis Langens]

"Andrew K. Mattei" wrote:
> 
> Well, I did a little more thinking, and some price lookup, and I think the
> Dual Port SRAM (from IDT or Cypress) puts us over our price target.
> 
> OK, new thought (for me). Standard SRAM. From DigiKey. $6.75 for a 1 Mbit
> 32-pin DIP. Still need all the buffer IC's I mentioned earlier [...]
>
> By using the above IC's, we can get the cost under $50

The lower tech / higher component count solution looks cheaper, but you
are forgetting to add several expenses.  There are Recurring Expenses
like sockets for all the buffers, a larger circuit board to hold all the
chips and perhaps even larger yet just to route all the connections,
time to solder all those pins, and time to troubleshoot for cold solder
joints and other assembly errors.  There are also some NREs like routing
a more complex board and checking the larger design.  Even though the
IDT and Cypress parts look expensive, they save more money elsewhere.

> One PIC, still, with a bunch (35?) of outputs

The PIC should be able to get away with A0 through A15/A16/Awhatever, D0
through D7, ~WE, ~OE, ~CS, one RAM bank select, one RAM/ROM select, TxD,
and RxD.  That's 31/32/whatever.  If the PIC ends up pin limited, then
something like the 74HC299 can be used on the data bus.  Note the bank
selects will be available in both true and complement form on the
outputs of the (required) D F/F's used to sync them to the ECM.

> Where does the ECM store the parameters that it
> "learns"? Is that in some sort of low-power RAM, that's maintained after the
> car is turned "off" (I know that they are retained)?

Yes.  The "always on" battery power input keeps a portion of the system
SRAM alive.

> How would those react
> to a sudden change in program without power cycling the ECM?

Most will just start "learning" the new setting.  A few may be actively
adjusted to the new program - every ECM I've looked at always pins the
BLMs to the min and max specified in the current PROM.  A few values
might get confused - perhaps something like the IAC home position.

  ..........

The dual port RAM vs. single port RAM w/ external muxes issue might be
moot.  I don't know what folks want in terms of FLASH, EEPROM, or EPROM.
 If the PIC needs to share these with the ECM, muxes might be needed anyway.

Hmmm, are there any FLASH or EEPROM chips with a JTAG boundary scan
port?  Such an interface can be used as a very slow second interface
port.  It wouldn't allow true dual port access, but writing FLASH isn't
a dual port type operation to begin with.  So how's this:

  Dual port SRAM w/ ECM read access and w/ PIC read/write access
  FLASH on the ECM's bus and w/ a JTAG interface to the PIC
  ECM boots from the FLASH
  Program changes are downloaded into the DPRAM (including an entire
    image for the first download after power up)
  Successful changes can be copied from the DPRAM into FLASH - the ECM
    executes out of DPRAM during this time

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/