Eprom Emulator

[steve ravet]

> The lower tech / higher component count solution looks cheaper, but you
> are forgetting to add several expenses.  There are Recurring Expenses
> like sockets for all the buffers, a larger circuit board to hold all the
> chips and perhaps even larger yet just to route all the connections,
> time to solder all those pins, and time to troubleshoot for cold solder
> joints and other assembly errors.  There are also some NREs like routing
> a more complex board and checking the larger design.  Even though the
> IDT and Cypress parts look expensive, they save more money elsewhere.

I agree.

> Hmmm, are there any FLASH or EEPROM chips with a JTAG boundary scan
> port?  Such an interface can be used as a very slow second interface
> port.  It wouldn't allow true dual port access, but writing FLASH isn't
> a dual port type operation to begin with.  So how's this:
> 
>   Dual port SRAM w/ ECM read access and w/ PIC read/write access
>   FLASH on the ECM's bus and w/ a JTAG interface to the PIC
>   ECM boots from the FLASH
>   Program changes are downloaded into the DPRAM (including an entire
>     image for the first download after power up)
>   Successful changes can be copied from the DPRAM into FLASH - the ECM
>     executes out of DPRAM during this time

This sounds like the best design to me.


-- 
Steve Ravet
ARM, INC
steve.ravet at arm.com
www.arm.com