68HC11s

[Ludis Langens]

Roger Heflin wrote:
> 
> On Sun, 27 Jun 1999, Ross Myers wrote:
> > Roger please explain this to me.
> > Firstly, are we assuming the 808/165 P4's are based on the F1?, if so why do
> > the 808/165 have a 52 pin CPU?, when the F1 is 68pin.

The 52 pin CPU (whatever we choose to call it) used in the 165/730/etc.
is not a 68HC11 variant.  It is missing several standard 'HC11 opcodes,
the interrupt vectors are different, and the I/O is totally different.

I'd go as far as saying it predates the 'HC11:  Motorola "previewed" the
first 'HC11 variant in 1984.  Based on Mot's preview to production
timetable for the 68K, volume production of the 'HC11 probably began in
'85 or even as late as '86.

The '165 was first used in an '86 model car which really means the fall
of '85.  Thus, volume production must have started in the summer of '85.
 I have a '165 here with such date codes.  Backing up further, the drop
dead date for the design cutover from the '6870 to the '7165 must have
been back in '84, or even earlier considering GM's 4 year design cycle. 
This means the '165 chip set was already in limited production in 83/84.

> > Secondly, The A/D ports, I've been looking at the disassembly of the BUA
> > PROM, and what I can't figure is the A/D channel selects. It just doesn't
> > work out the same as the F1. On the ROM, to select Ch7, you LDDA #$70 and
> > jump to the A/D sub. This value doesn't seem right, according to my 68HC11F1
> > book Ch7 would be selected by LDDA #$07.
> 
> I am not sure what you are talking about on the A/D selects, on the F1
> you write a #07 to $1030 to select channel 7, but generally I have
> notcied they don't select a single channel, they tell it to scan and
> load all of them and then read out the set of 4 registers.

In the 165/727/730/748/749/808/etc., the A/D is a seperate industry
standard chip on the SPI bus.  The upper four bits of the command byte
select one of 11 channels (or a 12th self test channel) for conversion. 
There is also a 19 channel version of this chip which uses the upper
five bits for a mux select.  Note that in the 727/730/749 GM uses a
seperate 8to1 analog mux feeding one of the 11 channels.  (Why didn't
they just use the bigger A/D?)

The SPI bus is full duplex.  Thus, at the same time as the command byte
is shifted out to the peripheral, a response byte is shifted in.  An A/D
conversion takes two of these transfers.  The first transmits the mux
select command (the received byte is ignored).  The second transfer
receives the conversion result (and a null command is sent).  Actually,
GM likes to send the self test command during the second transfer.  This
means that at the next A/D operation, the first received byte will be
for the self test channel.  This is sometimes checked and a code flagged.

Check the archives (diy_efi & gmecm) for a (partial) I/O map of the
165/727/730/748/749/808/etc.  Also check the '748 schematic on my web
pages.  The '748 is a reduced feature version of these other ECMs.

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/