Delayed ref pulse (was Re: Spark latency correction)

[Shannen Durphey]

Ward wrote:
> 
> On Sun, 19 Sep 1999 17:26:29 -0400, Shannen Durphey wrote:
> 
> > Ward wrote:
> >
> > > Please remember that spark advance is actuall dely, since yiu cant time
> > > travel backwards to start spark, its actualy delay from the prior TDC
> event.
> > > to calulate a V8 time between TDC's do 15/RPM,
> >
> > I've tried to see this by routing the REF to EST and applying 5V to
> > bypass.  I thought that I'd see a displaced timing mark with my timing
> > light, but it didn't happen.  What was I missing?
> > Shannen
> >
> 
> No. The delay in the processor won't be involved, and the inductive
> discharge is also not in that loop.
> 
> When you put by pass to +5 you switch the DRP output ckt from the coil
> driver to the DRP pin. You also disble the startup dwell and timing advance
> function. There is a 5 - 6 deg spark advance during by pass operation.
> 
> So I don't see how that would show the CPU indiced delay correction?
> 
> Ward
> 
Sorry, I wasn't clear.  I'm not looking for delay correction.  I'm
trying to recreate a display which used a distributor, a 2 channel
scope, and a coil to show the delayed pulse that timing is calculated
from.  I don't remember an ecm in the display, but possibly there
was.  I don't have the scope and I was hoping I could use a timing
light.

The 89 Vette I was using showed no difference in timing, as viewed at
the balancer, whether the ecm was running on base timing or ref pulses
looped back to the EST terminal.  I expected to see retarded timing.

Shannen