Kernel + real-time OS semantics

[Pat Ford]

 Why don't we first settle on a disassembler that takes an .inc file (
any suggestions??) and make a team effort? Who is interested??

"Malcolm Robb, LC 0112G" wrote:
> 
> What a great idea P4.inc would be. I'd also suggest including/using the
> variable and table names used in TurboP4.pdf too. That way anyone who knew
> how to understand one hac would be able to understand most others.
> 
> I have ....
> 
> LFFF0:  dw      $B000 ; SWI instruction
> LFFF2:  dw      $B34A ; ALDL interrupt vector & periodic timer
> LFFF4:  dw      $B59D ; External Interrupt Vector
> LFFF6:  dw      $B006 ; Illegal Instruction Interrupt Vector
> LFFF8:  dw      $B00A ; Bus Reset Vector (read or write 0x6000-0x6FFF)
> LFFFA: dw       $B00E ; Watchdog Vector
> LFFFC: dw       $B012 ; Clock Fail Vector
> LFFFE: dw       $B016 ; Reset Vector
> 
> Different assembler/disassembler I suppose. The irq1 vector is at $FFF2,
> called TMRVCT 
 TiMeR VeCtor the disassembler I use only takes 6 char for labels, thats
why I didn't do turboP4.pdf labels 


>in your nmenoics, and it is shared with the ALDL receive &
> transmit interrupts. The first thing the interrupt service routine does (in
> my code) is test some bits in a status register to ascertain what the cause
> of the interrupt is - ALDL RX, ALDL  TX or Heartbeat Timer as follows
> 
> ;**********************************************************************
> ;
> ; ALDL interrupt & periodic timer vector routine
> ;
> LB34A:  bset    NVRAMWD0, #NVRAMWD0_PEI
> 
>         ldX     #IOREG4000
>         brset   ALDL_REG,X,#ALDL_EXTIRQ,PERIODIC_IRQ
> 
>         brclr   SCI_CTRL,X,#SCI_RDRF, LB360     ; if SCI_RDRF enabled
>         brclr   ALDL_REG,X,#ALDL_RDRF,LB37E   ; and ALDL_RDRF occurred
>         call    ALDL_RX                 ; then next ALDL Rx'ed
>         reti
> ;
> LB360:  brclr   SCI_CTRL,X,#SCI_TDRE, LB36C     ; if SCI_TDRE enabled
>         brclr   ALDL_REG,X,#ALDL_TDRE,LB37E     ; and ALDL_TDRE occurred
>         call    ALDL_TX                 ; then Tx next ALDL byte
>         reti
> ;
> LB36C:  brclr   SCI_CTRL,X,#SCI_TC, LB37E       ; if SCI_TC enabled
>         brclr   ALDL_REG,X,#ALDL_TC,LB37E       ; and SCI_TC occurred
>                                                 ; then SCI Tx complete occurred
>         ldaA    #$27
>         staA    SCI_CTRL,X              ; 0x27 = enable SCI_RDRF & SCI_EXTIRQ & SCI_RE & SCI_RWU
> 
>         bclr    ALDLMW,#ALDLMW_TX       ; Flag ALDL inactive
>         bclr    IOPORTA,X,#SPI_ALDLTX   ; Disable the ALDL Tx Output Buffer
> 
> LB37E:  reti
> ;
> ;**********************************************************************
> 
> The jump table isn't at a fixed location for all code masks, so you'll need
> to specify which mask you're using to locate it. The table is buried within
> the main processor code. In my code ($B0 mask) it's at $D658
> 
> Hope this helps
> Push AF, Ret ;-)
> Malcolm
> 
> -----Original Message-----
> From:   Pat Ford [SMTP:pat at istop.com]
> Sent:   Wednesday, September 05, 2001 2:46 PM
> To:     gmecm at diy-efi.org
> Subject:        Re: Kernel + real-time OS semantics
> 
> where is the jump table? (on which mask??) which vector holds the address
> of irq1 ( the timer irq)
> does anyone have a list of what all the interrupt vectors are?
> i.e. this is what I have worked with
> FFF0    SWIVCT: .word   SWIVCT
> FFF2    TMRVCT: .word   TMRVCT
> FFF4    EXTVCT: .word   EXTVCT
> FFF6    ILL_OP: .word   SWIVCT
> FFF8    BUSVCT: .word   BUSVCT
> FFFA    COPVCT: .word   BUSVCT
> FFFC    CLKVCT: .word   BUSVCT
> FFFE    RSTVCT: .word   BUSVCT
> 
> does it look correct?
> what I think would be great is to pull together info and make a P4.inc
> file that has the defines for registers, int vectors .... That would
> help the disassemblies. I'll start trying to put one together today, if
> no one else wants to
> 
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