GM ALDL interface

[Ludis Langens]

Terry Kelley <terryk at foothill.net> wrote:
>No, I reprogrammed the time-of-day interrupt. That happens at a higher
>priority than anything else (relatively speaking). I then just need to
>service it at multiple intervals to keep the clock correct.
>
>So no matter what happened, every 500us ...
>
>Of course, the foreground program can get bogged down my other stuff, but
>this is real slow data rates. The floppy won't affect it and a network
>interrupt shouldn't unless they don't take over the interrupt correctly.

I guess the PC interrupt environment is different from a Mac.  Macs have
several situations where all interrupts (even "NMI" in some models!) are
disabled for extended intervals:  200 mS (one revolution) during flopppy I/O,
perhaps 400 mS (two revolutions) during floppy format, and 20 mS for a
LocalTalk (aka AppleTalk) packet.  Plus, the laptops tend to have their
own interrupt lockouts lasting several mS.


Terry Kelley <terryk at foothill.net> wrote:
>I looked for my lists of why a uart wouldn't work, but I can't find it. It
>was something subtle. It certainly wasn't a divisor issue, but something
>about 9 bit (1 start 8 bit) that wouldn't work.

A UART in a normal 160 baud async usage cannot receive the ALDL data because
the UART wants to eat both a start and a stop bit.  There is no way to get
it to eat the 1st (aka 9th) bit while passing the other 8 as a byte to your
CPU.  However, this is not the only way to use a UART!  In my idea, the
UART is simply used to sample the data line several times per each ALDL bit.
The parsing of the ALDL frame bits is performed in software.


Ron & Cathy Webb <cwebb at polarnet.com> wrote:
>I keep seeing referance to "one stop bit, 8 data bits, no parity"
>adding up to 9 bits. Can I be so old that I'm the only one who
>remembers that there is also a start bit?
>
>so an 8n1 data byte contains 10 bits, not 9! Unless the 160 ALDL
>is even wierder than I thought, which I suppose is entirely
>possible.

The UART stop, start and data bits are in a different realm than the ALDL
9 bit chunks.  For my idea, the UART could even be run in 5-N-1 mode.


Terry Kelley <terryk at foothill.net> wrote:
>And as far as I can remember, it is not pulse width modulated. It is 200uS
>sync bit, 3mS of data (0 or 1), and 3mS of logic 0 dead time, start again.
>If you put a scope on it and trigger on a falling edge (there is only one
>at the start of the sync bit), it is obvious.
>
>Unless there is a PWM 160 baud ECM, that is how it works.

What you just described _is_ a PWM scheme.  You could think of it as:
a "start" portion, a "data" (complemented in this case) portion, and a "stop"
portion.  But that is just the same as having a short pulse / long pulse
scheme - which is Pulse Width Modulated!  (I'd prefer to call the 160 ALDL a
PWM format, especially considering that the ECMs that I've hacked use a
digital one-shot to generate the ALDL signal.)


Perhaps a diagram might help clear up some confusion.  Here are two ALDL bits
(a total time interval of 2/160th of a second).  The UART "bits" are shown
beneath the waveform (S = Start, T = sTop, 0-8 = data).

    <------ ALDL "zero" bit ------> <------ ALDL "one" bit ------->
---+ +-----------------------------+                 +-------------+
   | |                             |                 |             |
   +-+                             +-----------------+             +-
. . S 0 1 2 3 4 5 6 7 T . . . . . . S 0 1 2 3 4 5 6 7 T . . . . . . S
      RxByte = 0xff                   RxByte = 0x00

An ALDL data packet would get received by the UART as this sequence of bytes:

  0,   0,     0,     0,     0,     0,     0,     0,     0,      {sync bits}
  255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255   {ALDL byte 1}
  255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255   {ALDL byte 2}
  255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255, 0|255   ...
  255, ...

                   unsigned long BinToBCD(unsigned long i) {unsigned long t;
Ludis Langens         return i ? (t = BinToBCD(i >> 1), (t << 1) + (i & 1) + 
ludis at netcom.com                 (t + 858993459 >> 2 & 572662306) * 3) : 0;}