[Diy_efi] Continuing the chip switcher "problem"

Wed Feb 16 08:05:30 GMT 2005

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Marcello,

I think I would tend to clock the address changes through the '374 using  not 
CE rather than not OE, but both would probably work just as well.  I  don't 
know any logic family (NMOS, CMOS, TTL, HCTTL etc) that would interpret  the 
logic level transitions you are seeing as going from logic 1 to logic  0.  There 
must be a potential difference between the ground you are picking  up for the 
scope probe and the logic ground the memory device is seeing.

I don't think your problem is grounding, I think it's just the address line  
transitions being visible during read cycles.

Is your DSO set to couple the signals through into the Y channel as a DC  
signal or as AC?
It should be set for a DC signal of course.

Will

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<HTML><HEAD>
<META http-equiv=3DContent-Type content=3D"text/html; charset=3DUS-ASCII">
<META content=3D"MSHTML 6.00.2900.2523" name=3DGENERATOR></HEAD>
<BODY id=3Drole_body style=3D"FONT-SIZE: 10pt; COLOR: #000000; FONT-FAMILY:=20=
Arial"=20
bottomMargin=3D7 leftMargin=3D7 topMargin=3D7 rightMargin=3D7><FONT id=3Drol=
e_document=20
face=3DArial color=3D#000000 size=3D2>
<DIV>Marcello,</DIV>
<DIV>&nbsp;</DIV>
<DIV>I think I would tend to clock the address changes through the '374 usin=
g=20
not CE rather than not OE, but both would probably work just as well.&nbsp;=20=
I=20
don't know any logic family (NMOS, CMOS, TTL, HCTTL etc) that would interpre=
t=20
the logic level transitions you are seeing as going from logic 1 to logic=20
0.&nbsp; There must be a potential difference between the ground you are pic=
king=20
up for the scope probe and the logic ground the memory device is seeing.</DI=
V>
<DIV>&nbsp;</DIV>
<DIV>I don't think your problem is grounding, I think it's just the address=20=
line=20
transitions being visible during read cycles.</DIV>
<DIV>&nbsp;</DIV>
<DIV>Is your DSO set to couple the signals through into the Y channel as a D=
C=20
signal or as AC?</DIV>
<DIV>It should be set for&nbsp;a DC signal of course.</DIV>
<DIV>&nbsp;</DIV>
<DIV>Will</DIV>
<DIV>&nbsp;</DIV></FONT></BODY></HTML>

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