EPROM Emulator Proposal

Wed Apr 7 13:28:43 GMT 1999

The EPROM emulator debate on this list seems to be going in circles. 
Either people have short memories, or there are a lot of new members who
missed the discussion and decisions made in the first few weeks of
gmecm.  Either way, please read through the archives.

Anyway, here is an emulator proposal based on the prior discussion.  I
did some ruthless cutting of features and expandability (indicated with
a *).  I propose the use of a single dual-port SRAM (from Cypress or
IDT) and a 40/44 pin PIC microcontroller to load this RAM.  A battery
back up will keep the SRAM alive.  This allows an ECM to boot from the
DPRAM immediately upon power-up.  The whole emulator circuit board
should be small enough to fit inside a '165/'727/'730/'749/'808 ECM.

The DPRAM is split into two banks.  The PIC can read and write in either
bank.  It also controls which bank the ECM reads.  This allows the ECM
to execute out of one bank while the PIC writes into the other bank. 
Once a download is finished, the ECM can be switched instantly to the
new bank.  A 64Kbyte DPRAM allows emulating up to a 27256 EPROM.  A
128Kbyte DPRAM emulates a 27512.

128Kbyte DPRAMs are currently only available in an impossible to hand
solder 100 TQFP package.  Smaller DPRAMs come in 84 PLCC packages.  The
TQFP package is so much smaller than the PLCC that we can make a dual
pattern circuit board with the TQFP inside the PLCC.  This allows most
people to use a PLCC DPRAM.  Those few who need to emulate a 27512 could
have a circuit board company solder on a TQFP chip (*).  Perhaps in half
a year a 128Kbyte DPRAM will also be available in PLCC.

This emulator will not emulate a 27C010 or any other 32 pin EPROM (*).

The PIC can communicate with a laptop computer using a MAX233.  That's a
MAX232 without the external capacitors (this saves board space).  The
PIC doesn't have enough I/O lines, so only TxD and RxD signals are
supported (*).  If data handshaking is needed, it will have to be with
XON and XOFF characters.

To prevent the ECM from reading indeterminate data, the ECM side bank
select needs to be syncronized with ECM memory access.  A latch
controlled by the OR of the ECM's ~CS and ~OE signals will suffice. 
This can be built with six simple gates in two 14 pin chips.  The OR
gate needs to be an HCT part.

An EPROM reader is included in this design.  This allows reading out the
original EPROM/MEMCAL contents without a seperate EPROM programmer.  The
EPROM can be accessed by the PIC.  To allow 'hot socketing', the PIC can
shut off the EPROM's power.  Note that the ECM _cannot_ read this EPROM.

A 66 pin plug (which plugs into a MEMCAL socket) connects the emulator
to an ECM.  A 66 pin socket allows a MEMCAL to be piggy-backed onto the
emulator.  All the non-EPROM MEMCAL pins are wired 1 to 1 between the
plug and socket.  There should be enough room to also have 0.3"/0.6"
wide sockets for resistor packs and a ESC module removed from a MEMCAL. 
Additionally, 0.6" 28 pin DIP socket patterns can straddle the EPROM
pins of both the 66 pin plug and socket.  The former allows the emulator
to have a header for non-MEMCAL applications.  The latter is for reading
a seperate EPROM.

The ECM's A0-A15, D0-D7, ~CS, and ~OE connect directly to one side of
the DPRAM.  The address lines are shifted up by one so that the DPRAM A0
can be used for the bank select.

The PIC connects to the DPRAM and piggybacked EPROM/MEMCAL as follows:

RA0..RA1  A14..A15 (DPRAM A15..A16)
RA2       PIC RAM bank select (DPRAM A0)
RA3       ECM RAM bank select (ECM side DPRAM A0 via latch)
RA4       EPROM power control (active low) (RA4 is open-collector)
RA5       EPROM ~CS

RB0..RB7  A0..A7 (DPRAM A1..A8)

RC0..RC5  A8..A13 (DPRAM A9..A14)
RC6       TxD
RC7       RxD

RD0..RD7  D0-D7

RE0       ~OE (DPRAM & EPROM)
RE1       ~WE (DPRAM R/~W)
RE2       DPRAM ~CS

For the battery back-up feature, all the DPRAM inputs will need 100K (or
so) ohm pulldown resistors.  The DPRAM has two chip select inputs on
each side.  The second input can be controlled by the battery back-up
circuit.  This circuit still needs to be designed.  I don't have access
to the latest power controller chip data.  I think someone had a
proposal for this.  Note that the DPRAM needs to be fed 5 volts even
during standby mode.  Also needed is a VCC switch for the EPROM.  I
think a single FET would work.

This emulator is meant to emulate 28 pin EPROMs from the 2764 through
the 27512.  A 24 pin to 28 pin adapter cable would allow emulation of
2732 EPROMs for the C3 folks.

Is there enough interest for me to draw up a schematic in a few days? 
Someone else will need to draw up the power supply circuitry.  Following
that, circuit board artwork will be needed (David?).  If we decide to
proceed with this design, I should have time to write some code for the
PIC in a month or two.  Right now my top priority is assembling an engine.

BTW, this is seperate from the RAMCAL idea I mentioned a while ago.  I'm
ready to write some CPLD equations for that - once my engine is running.

-- 
Ludis Langens                               ludis (at) cruzers (dot) com
Mac, Fiero, & engine controller goodies:  http://www.cruzers.com/~ludis/