VSS importance

[T Hergen]

If the ecm doesn't care about the duty cycle, you may be able to use
something simple (view with fixed width font):

                                  ________
                                ) )       )
   in     -----o-----------------) )       )
               |                  ) )       )---------- out
               |           ------) )       )
               |           |    ) )_______)
               |           |      poor excuse for a 74hc86 xor gate
               |           |
               -/\/\/\/----o----|(--- gnd
 
 
    Output will generate a pulse for each edge on the input.
    This doubles the average frequency.  The duty cycle will
    not be 50-50.
 
 
          _______________               _______________
in    ____|              |______________|              |_______
          ____           ____           ____           ____
out   ____|   |__________|   |__________|   |__________|   |___
 

The input signal should be buffered by one of the other four gates
in the 74hc86 package.

I haven't taken the time to calculate the resistor and cap values,
but can if you're interested.


Tom



On Mon, 28 Sep 1998 jdzura at csc.com wrote:

> The problem with doing a one-shot solution is the analog nature of the frequency
> multiplication. Over time and temperature there will most likely be problems. The
> classic way to do this is to implement a phase locked loop with a divide by 2
> (D-FF) in the feedback path to the phase comparator. The output of the PLL before
> the flip flop will be exactly 2x the input frequency. I  can't remember the
> series, but there used to be a 4000 series Cmos PLL that had great application
> notes.
> 
> The other purely "digital" way requires an oscillator to run a series of Flip
> flops that can be used to do the 2x frequency multiplication. This is essentially
> a zero order PLL. In either digital case, the circuit will take a few chips and
> some additional power. I believe I have read where someone sells an adapter for
> $50-60 already done. If it has been done and is only $50, you should probably buy
> it. Designing one will probably cost at least half that by the time you consider
> packaging, connectors, and a wirewrap board. Just my humble opinion and I have
> been an electronic designer for more than 15 years. If you still insist, let me
> know, and I will look up the reference to the cmos PLL chip. CMOS has the
> advantage of being run from 12 VDC and won't incur the overhead of voltage
> regulation.
> 
> Joe D
> 
> 
> 
> 
> 
> "Bruce Plecan" <nacelp at bright.net> on 09/28/98 01:48:00 PM
> 
> Please respond to diy_efi at efi332.eng.ohio-state.edu
> 
> To:   diy_efi at efi332.eng.ohio-state.edu
> cc:    (bcc: Joe Dzura/SED/CSC)
> Subject:  Re: VSS importance
> 
> 
> 
> 
> 
> -----Original Message-----
> From: Mike Hoenes <MHoenes at dhr.state.nc.us>
> To: Jake Sternberg <chickens at ccwf.cc.utexas.edu>;
> diy_efi at esl.eng.ohio-state.edu <diy_efi at esl.eng.ohio-state.edu>
> Date: Monday, September 28, 1998 1:00 PM
> Subject: RE: VSS importance
> 
> >anyone figure out how to get a 730  with a 91 L98 eprom to accept input
> from
> >a 2000ppm vss?
> 
> Been figuring but not done yet.
> I'm assuming you want a 4000ppm, and only have a 2000ppm.
> What I think will work is use two 555 as monostables.  Trigger
> one off the - edge of the input signal, and one off of the + edge,
> then combine the two signals with a 4011 or some such, tie
> that to a Mosfet, and a resistor off of that and use the resistor's
> input as the VSS signal.
> ______            ______            ______            ______
>              I_____I             I_____I             I_____I
> ______   ___    ____    _____    ____   ____    ____
>              I_I      I_I          I_I           I_I         I_I         I_I
> Hard to type with Doc laughing at my wave patterns
> Maybe some EE has input?.
> Cheers
> Bruce
> 
> 
> 
> 
> 
> 
>